1. Field of the Invention
The present invention relates to a display control apparatus for a portable computer, and, more particularly, to a technique of controlling the paging function of a coprocessor.
2. Description of the Related Art
As one of memory management schemes of a CPU, a virtual memory management (paging) is disclosed in U.S. Pat. No. 4,972,338 (titled "Memory Management for Microprocessor System," filed by Intel Corporation and registered on Nov. 20, 1990).
In protect mode of the Intel 80386 CPU or above, the paging function is supported. As shown in FIG. 1, linear addresses are freely associated with physical addresses in accordance with the contents of a table called "page table 10." The "linear address" is the value of an offset + segment base address.
The use of this paging function allows for virtual address translation and memory protection block (page frame) by block. Normally, executing the paging function requires two levels of page directories and page tables. The size of a page affects the performance/efficiency of paging. If the page size is small, there would be less waste in memory translation but many page tables would be required.
In a computer system, such a paging function is provided in various controllers which are capable of directly accessing the system memory, as well as in the CPU.
For instance, the display controller called "XGA (eXtended Graphics Array)," disclosed in "Video Subsystem," issued in 1989 and 1991 by International Business Machine Corporation, uses the paging function to be able to access the VRAM or directly access the system memory as a bus master. The coprocessor is provided with the paging function to maintain compatibility with the memory environment at the time the CPU performs paging. The address translation from a linear address to a physical address by the coprocessor built in the aforementioned XGA will now be briefly explained referring to FIGS. 1 through 4.
In the paging function, generally, a page size of 4 Kbytes is allocated per page and the head address of a page is a physical address whose bottom 12 bits are 0.
FIG. 2 presents a flowchart for address translation. To use the paging function, a page directory and a page table are placed on the system memory first. The physical address of the page directory (from the 31st bit to 12th bit of the physical address) is set in a page directory base address register (PDBR) of CR (control register) 3. Then, the PG bit of CR0 is set to enable this function (S10).
With the PG bit being 1, translation from a linear address to a physical address is carried out using virtual address translation (S20 to S30).
FIG. 3(a) illustrates how to translate a linear address to a physical address.
The linear address from the coprocessor is divided into three fields that are used to look up the corresponding physical address. The fields, called Page Directory Index 20, Page Table Index 30 and Offset 40, are illustrated in the linear address fields. The location of a page directory 60 is at a fixed physical address in memory that must be on a page (4 KB) address boundary. The coprocessor has a Page Directory Base address Register (PDBR) 50 that must be loaded with the address of the page directory base.
The Page Directory Index field of the linear address is used to index into the page directory 60. The entry read from the page directory contains 20-bit page table address and some statistical information in the low order bits.
The 20-bit page table address points to the base of a page table 70 in memory. The Page Table Index field in the linear address is used to index into the page table 70. The entry read from the page table 70 contains a 20-bit page address and some statistical information in the low order bits.
The 20-bit page address points to the base of a 4 KB page frame 80 in memory. The Offset field in the linear address is used to index into the page frame 80. The entry read from the page frame 80 contains the data required by the memory access.
The entries of the page directory 60 and page table 70 are very similar. The format of an entry is shown in FIG. 3(b).
The coprocessor in the XGA has its own internal cache of translated addresses to avoid its having to perform the two-stage translation process on every coprocessor access. This cache is referred to as a Translated Look-aside Buffer (TLB).
The TLB has two entries, one entry for the source, pattern and mask PEL maps, and the other for the destination PEL map, as shown in FIG. 4. Each entry is reserved specifically for use by one of these maps. Each entry in the TLB contains the top 20 bits of a linear address tag 90, an entry valid flag bit and the top 20 bits of the physical address corresponding to that linear address. In the case of the virtual address translation from the coprocessor, first the top 20 bits of the linear address are compared against the appropriate linear address tag 90 of the TLB. If they match, the it is determined if valid flag bit 100 of the TLB is "1." If the valid flag bit 100 is "1," called a TLB hit, the real page address is used with the bottom 12 bits of the linear address, called the offset, used as the 12 bits of the physical address. If the tag does not match, a TLB mishit occurs.
In the case of the coprocessor incorporated in the aforementioned XGA, however, paging lowers the drawing performance, such as graphics drawing and block transfer (BITBLT) for the following reason. A VRAM is memory with a large capacity of 4 Mbytes. If paging of 4 Kbytes per page is performed to this memory, a TLB mishit occurs for every 4-line drawing for a screen with each single line consisting of 1024 dots and 8 bits per pixel in the case where a straight line is drawn in the vertical direction. When a TLB mishit occurs, virtual address translation should be executed referring to the page table in the system memory and data renewal (flush) of the TLB is also required. Consequently, the speed of accessing the VRAM substantially decreases.
Since the conventional coprocessor having the paging function utilizes the paging function for the system memory directly to access the VRAM, the drawing performance is considerably reduced depending on what is to be drawn in the VRAM.
In other words, according to the prior art, the drawing performance to the VRAM is reduced by the occurrence of multiple TLB mishits.